/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2021 Huawei Technologies Co., Ltd */

#ifndef HINIC3_CSR_H
#define HINIC3_CSR_H

/* bit30/bit31 for bar index flag
 * 00: bar0
 * 01: bar1
 * 10: bar2
 * 11: bar3
 */
#define HINIC3_CFG_REGS_FLAG			0x40000000

#define HINIC3_MGMT_REGS_FLAG			0xC0000000

#define HINIC3_REGS_FLAG_MAKS			0x3FFFFFFF

#define HINIC3_VF_CFG_REG_OFFSET		0x2000

#define HINIC3_HOST_CSR_BASE_ADDR		(HINIC3_MGMT_REGS_FLAG + 0x6000)
#define HINIC3_CSR_GLOBAL_BASE_ADDR		(HINIC3_MGMT_REGS_FLAG + 0x6400)

/* HW interface registers */
#define HINIC3_CSR_FUNC_ATTR0_ADDR		(HINIC3_CFG_REGS_FLAG + 0x0)
#define HINIC3_CSR_FUNC_ATTR1_ADDR		(HINIC3_CFG_REGS_FLAG + 0x4)
#define HINIC3_CSR_FUNC_ATTR2_ADDR		(HINIC3_CFG_REGS_FLAG + 0x8)
#define HINIC3_CSR_FUNC_ATTR3_ADDR		(HINIC3_CFG_REGS_FLAG + 0xC)
#define HINIC3_CSR_FUNC_ATTR4_ADDR		(HINIC3_CFG_REGS_FLAG + 0x10)
#define HINIC3_CSR_FUNC_ATTR5_ADDR		(HINIC3_CFG_REGS_FLAG + 0x14)
#define HINIC3_CSR_FUNC_ATTR6_ADDR		(HINIC3_CFG_REGS_FLAG + 0x18)

#define HINIC3_FUNC_CSR_MAILBOX_DATA_OFF	0x80
#define HINIC3_FUNC_CSR_MAILBOX_CONTROL_OFF		\
			(HINIC3_CFG_REGS_FLAG + 0x0100)
#define HINIC3_FUNC_CSR_MAILBOX_INT_OFFSET_OFF		\
			(HINIC3_CFG_REGS_FLAG + 0x0104)
#define HINIC3_FUNC_CSR_MAILBOX_RESULT_H_OFF		\
			(HINIC3_CFG_REGS_FLAG + 0x0108)
#define HINIC3_FUNC_CSR_MAILBOX_RESULT_L_OFF		\
			(HINIC3_CFG_REGS_FLAG + 0x010C)
/* CLP registers */
#define HINIC3_BAR3_CLP_BASE_ADDR		(HINIC3_MGMT_REGS_FLAG + 0x0000)

#define HINIC3_UCPU_CLP_SIZE_REG	(HINIC3_HOST_CSR_BASE_ADDR + 0x40)
#define HINIC3_UCPU_CLP_REQBASE_REG	(HINIC3_HOST_CSR_BASE_ADDR + 0x44)
#define HINIC3_UCPU_CLP_RSPBASE_REG	(HINIC3_HOST_CSR_BASE_ADDR + 0x48)
#define HINIC3_UCPU_CLP_REQ_REG		(HINIC3_HOST_CSR_BASE_ADDR + 0x4c)
#define HINIC3_UCPU_CLP_RSP_REG		(HINIC3_HOST_CSR_BASE_ADDR + 0x50)
#define HINIC3_CLP_REG(member)		(HINIC3_UCPU_CLP_##member##_REG)

#define HINIC3_CLP_REQ_DATA		HINIC3_BAR3_CLP_BASE_ADDR
#define HINIC3_CLP_RSP_DATA		(HINIC3_BAR3_CLP_BASE_ADDR + 0x1000)
#define HINIC3_CLP_DATA(member)		(HINIC3_CLP_##member##_DATA)

#define HINIC3_PPF_ELECTION_OFFSET		0x0
#define HINIC3_MPF_ELECTION_OFFSET		0x20

#define HINIC3_CSR_PPF_ELECTION_ADDR		\
			(HINIC3_HOST_CSR_BASE_ADDR + HINIC3_PPF_ELECTION_OFFSET)

#define HINIC3_CSR_GLOBAL_MPF_ELECTION_ADDR		\
			(HINIC3_HOST_CSR_BASE_ADDR + HINIC3_MPF_ELECTION_OFFSET)

#define HINIC3_CSR_FUNC_PPF_ELECT_BASE_ADDR	(HINIC3_CFG_REGS_FLAG + 0x60)
#define HINIC3_CSR_FUNC_PPF_ELECT_PORT_STRIDE	0x4

#define HINIC3_CSR_FUNC_PPF_ELECT(host_idx)	\
	(HINIC3_CSR_FUNC_PPF_ELECT_BASE_ADDR +	\
	 (host_idx) * HINIC3_CSR_FUNC_PPF_ELECT_PORT_STRIDE)

#define HINIC3_CSR_DMA_ATTR_TBL_ADDR		(HINIC3_CFG_REGS_FLAG + 0x380)
#define HINIC3_CSR_DMA_ATTR_INDIR_IDX_ADDR	(HINIC3_CFG_REGS_FLAG + 0x390)

/* MSI-X registers */
#define HINIC3_CSR_MSIX_INDIR_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x310)
#define HINIC3_CSR_MSIX_CTRL_ADDR		(HINIC3_CFG_REGS_FLAG + 0x300)
#define HINIC3_CSR_MSIX_CNT_ADDR		(HINIC3_CFG_REGS_FLAG +	0x304)
#define HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR		(HINIC3_CFG_REGS_FLAG + 0x58)

#define HINIC3_MSI_CLR_INDIR_RESEND_TIMER_CLR_SHIFT	0
#define HINIC3_MSI_CLR_INDIR_INT_MSK_SET_SHIFT		1
#define HINIC3_MSI_CLR_INDIR_INT_MSK_CLR_SHIFT		2
#define HINIC3_MSI_CLR_INDIR_AUTO_MSK_SET_SHIFT		3
#define HINIC3_MSI_CLR_INDIR_AUTO_MSK_CLR_SHIFT		4
#define HINIC3_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_SHIFT	22

#define HINIC3_MSI_CLR_INDIR_RESEND_TIMER_CLR_MASK	0x1U
#define HINIC3_MSI_CLR_INDIR_INT_MSK_SET_MASK		0x1U
#define HINIC3_MSI_CLR_INDIR_INT_MSK_CLR_MASK		0x1U
#define HINIC3_MSI_CLR_INDIR_AUTO_MSK_SET_MASK		0x1U
#define HINIC3_MSI_CLR_INDIR_AUTO_MSK_CLR_MASK		0x1U
#define HINIC3_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_MASK	0x3FFU

#define HINIC3_MSI_CLR_INDIR_SET(val, member)		\
		(((val) & HINIC3_MSI_CLR_INDIR_##member##_MASK) << \
		HINIC3_MSI_CLR_INDIR_##member##_SHIFT)

/* EQ registers */
#define HINIC3_AEQ_INDIR_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x210)
#define HINIC3_CEQ_INDIR_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x290)

#define HINIC3_EQ_INDIR_IDX_ADDR(type) \
		((type == HINIC3_AEQ) ? \
		HINIC3_AEQ_INDIR_IDX_ADDR : HINIC3_CEQ_INDIR_IDX_ADDR)

#define HINIC3_AEQ_MTT_OFF_BASE_ADDR		(HINIC3_CFG_REGS_FLAG + 0x240)
#define HINIC3_CEQ_MTT_OFF_BASE_ADDR		(HINIC3_CFG_REGS_FLAG + 0x2C0)

#define HINIC3_CSR_EQ_PAGE_OFF_STRIDE			8

#define HINIC3_AEQ_HI_PHYS_ADDR_REG(pg_num)	\
		(HINIC3_AEQ_MTT_OFF_BASE_ADDR + \
		(pg_num) * HINIC3_CSR_EQ_PAGE_OFF_STRIDE)

#define HINIC3_AEQ_LO_PHYS_ADDR_REG(pg_num)	\
		(HINIC3_AEQ_MTT_OFF_BASE_ADDR + \
		(pg_num) * HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4)

#define HINIC3_CEQ_HI_PHYS_ADDR_REG(pg_num)	\
		(HINIC3_CEQ_MTT_OFF_BASE_ADDR + \
		(pg_num) * HINIC3_CSR_EQ_PAGE_OFF_STRIDE)

#define HINIC3_CEQ_LO_PHYS_ADDR_REG(pg_num)	\
		(HINIC3_CEQ_MTT_OFF_BASE_ADDR + \
		(pg_num) * HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4)

#define HINIC3_CSR_AEQ_CTRL_0_ADDR		(HINIC3_CFG_REGS_FLAG + 0x200)
#define HINIC3_CSR_AEQ_CTRL_1_ADDR		(HINIC3_CFG_REGS_FLAG + 0x204)
#define HINIC3_CSR_AEQ_CONS_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x208)
#define HINIC3_CSR_AEQ_PROD_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x20C)
#define HINIC3_CSR_AEQ_CI_SIMPLE_INDIR_ADDR	(HINIC3_CFG_REGS_FLAG + 0x50)

#define HINIC3_CSR_CEQ_CTRL_0_ADDR		(HINIC3_CFG_REGS_FLAG + 0x280)
#define HINIC3_CSR_CEQ_CTRL_1_ADDR		(HINIC3_CFG_REGS_FLAG + 0x284)
#define HINIC3_CSR_CEQ_CONS_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x288)
#define HINIC3_CSR_CEQ_PROD_IDX_ADDR		(HINIC3_CFG_REGS_FLAG + 0x28c)
#define HINIC3_CSR_CEQ_CI_SIMPLE_INDIR_ADDR	(HINIC3_CFG_REGS_FLAG + 0x54)

/* API CMD registers */
#define HINIC3_CSR_API_CMD_BASE			(HINIC3_MGMT_REGS_FLAG + 0x2000)

#define HINIC3_CSR_API_CMD_STRIDE		0x80

#define HINIC3_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)	\
	(HINIC3_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)	\
	(HINIC3_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_STATUS_HI_ADDR(idx)		\
	(HINIC3_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_STATUS_LO_ADDR(idx)		\
	(HINIC3_CSR_API_CMD_BASE + 0xC + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)	\
	(HINIC3_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)		\
	(HINIC3_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_CHAIN_PI_ADDR(idx)		\
	(HINIC3_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_CHAIN_REQ_ADDR(idx)		\
	(HINIC3_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

#define HINIC3_CSR_API_CMD_STATUS_0_ADDR(idx)		\
	(HINIC3_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC3_CSR_API_CMD_STRIDE)

/* self test register */
#define HINIC3_MGMT_HEALTH_STATUS_ADDR (HINIC3_MGMT_REGS_FLAG + 0x983c)

#define HINIC3_CHIP_BASE_INFO_ADDR (HINIC3_MGMT_REGS_FLAG + 0xB02C)

#define HINIC3_CHIP_ERR_STATUS0_ADDR (HINIC3_MGMT_REGS_FLAG + 0xC0EC)
#define HINIC3_CHIP_ERR_STATUS1_ADDR (HINIC3_MGMT_REGS_FLAG + 0xC0F0)

#define HINIC3_ERR_INFO0_ADDR (HINIC3_MGMT_REGS_FLAG + 0xC0F4)
#define HINIC3_ERR_INFO1_ADDR (HINIC3_MGMT_REGS_FLAG + 0xC0F8)
#define HINIC3_ERR_INFO2_ADDR (HINIC3_MGMT_REGS_FLAG + 0xC0FC)

#define HINIC3_MULT_HOST_SLAVE_STATUS_ADDR (HINIC3_MGMT_REGS_FLAG + 0xDF30)
#define HINIC3_MULT_MIGRATE_HOST_STATUS_ADDR (HINIC3_MGMT_REGS_FLAG + 0xDF4C)
#define HINIC3_MULT_HOST_MASTER_MBOX_STATUS_ADDR HINIC3_MULT_HOST_SLAVE_STATUS_ADDR

#endif
